Scatterometry for Gate-All-Around (GAA) Technology Enablement

Authored by: Anne-Laure Charley 1, Hans Mertens 1, Naoto Horiguchi 1, Phillipe Leray 1, Matthew Sendelbach 2, Nivea Figueiró 3, Roy Koret 4, Shay Wolfling 4, Avron Ger 4 Christopher Hakala 5, Jason Arjavac 5 | SPIE 2017, February 1, 2017

The future of logic silicon extension lies at the heart of Gate-All-Around (GAA) developments (1). Due to the increasing limitations in further FinFET flow extension, research groups worldwide are fabricating vertical and horizontal nanowire (NW) integration schemes. The horizontal NW are of great interest due to their integration similarity to the existing FinFET integration flow (2). This in turn allows to extend the usage of existing process and metrology platforms and reduce the cost of shifting to a new technology. Though the integration changes seem to be limited, they spring numerous new obstacles for fab metrology. As new parameters of interest emerge, the metrology capability needs to achieve higher performance and develop new solution methods (3) (4).
This paper focuses on several key process steps that are different from the FinFET process flow and discusses the OCD (Optical Critical Dimension) scatterometry capabilities. At the nanowire release step, a SiGe dummy layer is removed by dry etching, leaving the active silicon nanowires. Detailed metrology of these nanowire profiles and thicknesses is required to make sure that the device can perform to the expected specifications. To examine the scatterometry performance of this application, a Design of Experiment (DoE) was created at multiple process steps.
At the fin formation process step, we describe a DoE condition of applying silicon – silicon germanium (Si-SiGe) multi-layer deposition splits where the SiGe layer thicknesses are changed between wafers. It is further shown how scatterometry can be used to sustain the X-Ray Reflectivity (XRR) accuracy and ensure higher sampling capability. A fin-reveal DoE was used to alter the total recess depth, allowing the lower SiGe layer to be revealed in varying amounts in the preparation for the later SiGe release etching step. We discuss a process condition where an Atomic Force Microscope (AFM) and scatterometry can both be used as well as demonstrate a condition where AFM has limited capabilities and one can only use scatterometry. The final process reported in this paper is the Nanowire Release (NW Release) etching method in which the SiGe is released while the silicon NW remains. The DoE consists of two etching methods, each providing a different NW profile. We explain how scatterometry can monitor the nanowire profile by using a specific target design. Finally, we discuss the improved accuracy that becomes possible owing to the Transmission Electron Microscopy (TEM) rich sampling.
Keywords: scatterometry, Gate-All-Around, GAA, Nanowire Release, XRR, AFM, TEM.