Advanced Logic Device Architectures – Challenges and Solutions in Materials Metrology

Today's most advanced AI processors consist of billions of transistors and are steadily growing toward 1 trillion. Earlier this year, NVIDIA announced on the arrival of their new Blackwell platform, to power a new era of computing. Its GPU, the world’s most powerful chip, is packed with not less than 208 billion transistors! These tiny components are the stars of semiconductors, but behind every high-performance transistor lies a multitude of materials involved in the fabrication process.

We have been in the materials era for several years now, and this trend is expected to continue into the foreseeable future. The primary reason for this is that traditional scaling and even 3D architectures are no longer sufficient for creating high-performance devices. As a result, new materials are being introduced, with nearly the entire periodic table being utilized in IC production.

Various novel materials are employed in IC manufacturing. The fundamental ones include Silicon (Si), Germanium (Ge), oxidants, and dopants. These are the basic building blocks of semiconductors and have the greatest impact on their performance. Additionally, sacrificial materials such as photoresists, developers, cleaners, surfactants, and others are used during the different wafer processing stages.

In this post, we will explore the trends, challenges, and solutions related to the increasing use of materials in advanced logic devices, with a focus on the fundamental "construction" materials that define their performance.

Materials in Advanced Logic Devices

Examining the history of logic device development, often referred to as "the scaling roadmap," reveals the critical role materials have played in its evolution. Nearly every new technology node has introduced new materials, processes and architectures, ranging from copper and Silicon-Germanium (SiGe) to High-K Metal Gate (HKMG), cobalt, lanthanum, dipole materials, and potentially 2D materials in the future. Here are two notable examples.

The Impact of Materials on Logic Scaling Roadmap

Cu Dual Damascene– In the mid-1990s, IBM unveiled the world's first devices using a copper dual damascene process. Copper replaced the aluminum-based Back End of Line (BEOL) interconnect metal, significantly enhancing speed due to its much higher conductivity. One drawback of copper was its inability to be etched, preventing the use of subtractive patterning. This led to the development of the damascene process and additive patterning. The dual damascene process is employed to create and connect metallization layers. In this process, a via hole and a trench are etched and then filled with copper, hence the term "dual damascene."

High-K Metal Gate (HKMG)—In 2007, Intel introduced a significant innovation in the fabrication of 45 nm microprocessors. The transistor’s gate dielectric, a silicon dioxide insulator, began to lose its insulating quality and exhibit excessive leakage. Intel's solution was to replace silicon dioxide with a hafnium-based dielectric layer and use an alternative metal material for the gate electrode. This combination resulted in a "high dielectric constant," also known as "high-K."

Logic Roadmap and Challenges

Gate-All-Around (GAA) Centric Roadmap

Looking ahead at the roadmap for logic devices, despite many challenges, the path appears clear for at least the next decade. Already in production and in the coming years, the focus will be on GAA and its variants. This will evolve from the current 3-4 nanosheets to possibly the Forksheet design, which features a dielectric wall between PMOS and NMOS, allowing N and P to be closer for higher scaling, albeit with the drawback of losing one side of the GAA. The next significant advancement, already in development, is CFET, with NMOS over PMOS, offering additional scaling opportunities In fact, at the 2024 IEEE Symposium on VLSI Technology & Circuits (2024 VLSI), imec, a world-leading research and innovation hub in nanoelectronics and digital technologies, presented for the first time electrically functional CMOS CFET devices with stacked bottom and top source/drain contacts (see full details here: https://www.imec-int.com/en/press/imec-demonstrates-functional-monolithic-cfet-devices-stacked-bottom-and-top-contacts). In the future, we can expect to see much more integration of 2D materials into the architecture.

Logic GAA Centric Roadmap

GAA Process Flow Challenges

Zooming into the GAA process flow reveals several material challenges at key process steps that directly inflict on the operational characteristics of the transistor and its performance. Let's explore some of these challenges in detail to better understand the material characteristics that require close monitoring and control.

Source/Drain epitaxial growth (step e) - The concentration of Germanium and dopants (Boron for PFET and Phosphorus for NFET) must be controlled as it will determine the electrons and holes mobility in the transistor, and consequently its switching speed.

Gate spacer and nanosheets inner spacers formation (steps a and d) – Both are made of low K (<5) material reducing the parasitic capacitance between the gate and source/drain and preventing current leakage between the source and the drain. Therefore, the gate spacers need to be conformal and the Inner Spacers to fill the gaps completely. Both should be also etch tolerant.

Dielectric walls and interlayer (steps f and i) – Material properties are critical here as this dielectric provides electrical isolation between adjacent transistors across the entire wafer and prevents cross-interference as well as interlayer isolation between the frontend (transistors) and backend (metallization layers)

High-K metal gate formation (step h) – As mentioned earlier, HKMG was introduced to address the excessive gate current leakage problem. Both the application of the hafnium-based dielectric layer and metal layer (constructed of various metals) must be optimized as it is directly correlated to transistor’s electrical performance.

Simplified GAA Process Flow (Source: [1])

These are only few examples; there is a wide variety of material-related challenges in other GAA process steps. Looking ahead, as 2D materials are integrated into the process, the logic architecture may remain largely similar, but the materials and related challenges will increase and become significantly different.

Materials Metrology Solutions

Alongside the increase in the types of materials used, the range of important material properties is also expanding. These include factors such as stress, doping levels, interfaces, and many more. This significant trend directly impacts the scope of metrology, which is also expanding.

Metrology Technologies Characterization

To address emerging process challenges, a wide variety of materials metrology technologies are available for material characterization. Each technology offers different capabilities in terms of spot size and detection limits and can be categorized based on the type of information it provides (elemental, imaging, etc.). They can also be grouped by their "fab adoption" status: those deeply rooted in materials R&D labs, those used near the production lines (near-line), and the few that have transitioned to true in-line material metrology technologies.

metrology technologies characterized by information provided (right) and fab adoption (left); Adopted from Eurofins | EAG Laboratories

One key reason for the low adoption rate of lab technologies in fabs is the complexity and difficulty of migrating technology from the lab to high-volume manufacturing (HVM), which requires numerous innovations and modifications.

Firstly, the technology needs to be automated, encompassing hardware, software, mechanics, recipe-driven process flows, and automatic calibrations. For metrology technology to measure product wafers and be HVM-worthy, it must ensure fab connectivity, process control layers, tool-to-tool matching, and stability across various environmental conditions. Lastly, it must meet the performance requirements for advanced devices, which involve higher throughput, improved accuracy and repeatability, enhanced algorithms, data analysis tools to extract quantitative information, and the development of relevant application use cases.

Metrology Solutions for GAA Process Challenges

Let us examine two metrology technologies that were successfully migrated from the lab to the fab and how they solve unique challenges in the GAA process flow.

Dopant Concentration – SIMS on GAA Structure

In this example, SIMS (Secondary Ion Mass Spectrometry) is employed to monitor dopant concentrations in NFETs after the source/drain (S/D) of Silicon-Phosphorus (SiP) is grown around the fins. The analysis is based on a Design of Experiment involving various GAA widths. For all structures with differing Nanosheet widths, the positions of the silicon fins can be identified using the Germanium signal from the sacrificial SiGe superlattice layers. However, the phosphorus (P) doping concentration varies as the GAA width decreases, eventually leading to failure detection where the S/D fails to connect the Nanosheets.

Qualitative dopant concentration measurement using In-Line SIMS

Monitoring the dopant material profile on the structure is critical. By correlating this with dimensional data from OCD measurements, we can obtain quantitative results on the structure.

Strain Evolution – Raman Spectroscopy

In this example, Raman spectroscopy is used to monitor the silicon strain throughout the GAA process, which is highly correlated with the device's performance. The first graph on the left shows that the strain increases in the initial steps of the process and relaxes following the SiGe release for the small Fin Critical Dimension (gate length). The graph on the right focuses on the SiGe release step, demonstrating that the silicon channel stress can be tuned by controlling the Germanium concentration in the sacrificial SiGe layers.

Strain Evolution monitoring using Raman Spectroscopy

These are 2 examples only but there are many more challenges and additional capabilities for various in-line material metrology solutions. To mention a few:

XPS (X-Ray Photoelectron) spectroscopy is a surface-sensitive method that is used in-line for thickness and composition monitoring, and for residue detection in combination with XRF (X-ray Fluorescence).

Raman spectroscopy is used not only for strain but also for phase and crystallinity and average dopant concentration.

SIMS, which is starting its inline journey, is the ultimate measurement technique for material depth profiling and dopant and interface control.

EDS (Energy Dispersive Spectroscopy) capability on TEM (Transmission Electron Microscopy) is a powerful visualization tool for monitoring the thickness and composition of complex 3D structures during R&D and HVM.

The table below outlines the key various measurement and profiling capabilities of these four metrology technologies.

Inline Materials Metrology Solutions for GAA Process Control 

Taking it one step further – Hybrid Metrology

While this blog has focused on material properties and challenges, dimensions and material properties are intricately linked in complex 3D device architectures. Physical modeling and AI can jointly address these cross-metrology challenges.

One such example is SiGe recess measurement. As shown below, we measure the variation in an XRF signal before and after SiGe recess. Once quantified through TEM calibration, this variation serves as input for average SiGe recess measurement via OCD (Optical Critical Dimension). Here, AI and XRF's material property sensitivities are used to calibrate and significantly enhance dimensional measurements.

(Source: D. Schmidt et al., IEEE TSM, 2022)

Materials have played and will continue to play a crucial role in advancing the roadmap for Advanced Logic devices. The introduction of innovative architectures and structures relies heavily on materials innovation, driving a broader array of fabrication processes and related metrology.

Numerous powerful material metrology techniques exist but integrating them into fabrication processes ("Fab-friendly") is complex and challenging. Notable examples successfully integrated in-line include XPS, Raman spectroscopy, and SIMS. As metrology innovation expands, the list will grow. Moreover, recognizing that material and dimensional challenges are interconnected, AI and modeling are leveraged to address them comprehensively.

Images credit:

[1] ResearchGate: Study of Silicon Nitride Inner Spacer Formation in Process of Gate-all-around Nano-Transistors