From Transistors to a Complete System in Package – The 3D Evolution in Semiconductors’ Architecture

The semiconductor industry shapes the very fabric of our technological age, influencing nearly every aspect of our daily lives and driving the global economy. Whether it's the smartphones we use casually or the High-Power Computing (HPC) systems powering cutting-edge Generative AI applications, powerful semiconductor chips lie at the heart of it all. These chips, comprised of numerous miniature semiconductor components, particularly transistors, are marvels of modern engineering.

 Just how complex and densely packed are these chips? Consider the A17 Pro, a 64-bit ARM-based system on a chip (SoC) developed by Apple for the iPhone 15 Pro, boasting an astounding 19 billion transistors. And then there's NVIDIA's H100, hailed as the world's most advanced chip, featuring a mind-boggling 80 billion transistors! Such ultra-high-scale integration has been made possible through years of relentless miniaturization of semiconductor components, resulting in reduced space and power consumption, thereby enabling the integration of larger devices that comprise these formidable systems.

However, despite these remarkable advancements, the semiconductor industry faces a host of challenges that could potentially impede or restrict the ongoing miniaturization process, which aligns with Moore's Law. First articulated by Gordon Moore in 1965, Moore's Law observes that the number of transistors in an integrated circuit (IC) doubles approximately every two years, corresponding to the introduction of new technology nodes. The sustainability of Moore's Law is a perennial question, that has been raised before and is likely to resurface.

In response to these challenges and to foster continued technological growth, scientists and engineers continuously push the boundaries of semiconductor technology through innovative designs and structural enhancements. A prominent trend in this evolutionary journey is the adoption of 3D structures in advanced technology nodes and, most recently, in advanced packaging. In this post, we’ll briefly review the 3D evolution occurring at the component, device, and system levels of semiconductor chips.

3D Components Evolution

The transistor, the cornerstone of semiconductor design, has encountered physical limitations with the Planar transistor around the 28 nm technology node. Shrinking the transistor's channel and gate at this stage degraded its performance, necessitating innovative designs. This led to the introduction of the FinFET and, later, the Nanosheet (Gate-All-Around) transistor. While this evolution did not curb the rise in transistor costs in advanced technology nodes (16 nm and beyond), it facilitated further enhancements in performance, particularly in switching speed and current density. The transistor's 3D evolution beyond Nanosheet continues in R&D with the future “true 3D” CFET (nFET over pFET).

In the Memory segment, specifically DRAM, the bit cell, comprising two fundamental components—the transistor and a storage capacitor (1T1C)—is undergoing a similar evolution. It represents the second design evolution after the initial developments in the '70s and '80s. The storage capacitor has evolved from its initial Planar structure in 2 different paths – the trench (barried) capacitor and the stacked capacitor, that eventually, years later, privailed. It’s Cylinder structure was gradually formed in order to maintain sufficient capacitance as feature size is reduced. This evolution necessitated introducing new high-K dielectric materials to achieve desired capacitance values.

With the capacitor's geometry fixed on the cylinder shape, the focus shifted to minimizing the bit cell size and structure in order to maximize the overall memory capacity. It evolved (shrank) from 8F² to 6F² (F = Feature Size), with its capacitor becoming narrower and taller (Pillar-like) with the introduction of each new technology node. The industry is now moving toward a 4F² size cell featuring a vertical capacitor on top of a vertical channel transistor (VCT).

3D Devices Evolution - Memory

Moving on to the device level, let's have a look at the memory segment and continue with the DRAM evolution. While the above-mentioned 4F² architecture makes the memory cell smaller from an area standpoint, the capacitor consumes a lot of vertical space. The proposed solution to the ongoing capacitance challenge is to flip the cell onto its side, with the capacitors now oriented horizontally. This approach paves the way to a “single device” 3D DRAM, as the memory cells can be now stacked to form a tall vertical structure. This will require enough layers on this type of 3D DRAM to offset the increase in the lateral footprint in order to make it cost-effective.

Samsung Electronics recently shared a technology roadmap presented at Memcom, Link- https://semiwiki.com/forum/index.php?threads/samsung-announces-plans-for-3d-dram-development-with-sub-10nm-technology.19973/

in which 2D DRAMs featuring VCTs and 4F² cell design are expected to emerge in 2027–2028. Samsung also plans to adopt a 3D stacked DRAM process technology sometime in the early 2030s. Meanwhile, 3D DRAM in the form of High Bandwidth Memory (HBM) is already a reality, achieved through system-level (packaging) integration.

There’s currently a high focus on 3D DRAM evolution, following NAND Flash memory's transformation to 3D, which is used in smartphones, tablets, and storage devices like SSDs.

In 3D NAND Flash, memory cells are already stacked vertically in layers, allowing for increased capacity within a smaller footprint, thus significantly reducing the cost-per-byte. Vertical stacking also enables shorter connection paths between the layers, leading to lower latency and higher performance. However, manufacturing this memory stack presents a major challenge due to the high aspect ratio etching of the channel area. This is addressed by further vertical expansion through the creation of multi-deck structures.

3D System-On-Chip Evolution

The cost associated with leading-edge nodes, combined with the lack of scaling of significant design blocks and die sizes reaching reticle size, is driving the disaggregation of chip functions into their most cost-effective nodes for performance. This necessitates new technologies to interconnect these functions. In response to this new reality of a fragmented "wafer economy," semiconductor manufacturers are gradually transitioning towards a "packaging economy" through advanced packaging and, specifically, heterogeneous integration.

Heterogeneous Integration involves combining devices from different technology nodes to form a complete System in a Package (SiP). Similar to 3D devices, transitioning from a horizontally integrated 2D and 2.5D architecture to a vertically integrated 3D architecture reduces package size and improves performance metrics such as latency and power dissipation.

A notable example of such 3D system integration is HBM (High-Bandwidth Memory), mentioned earlier. HBM is a standardized stacked memory technology that provides wide data channels both within the stack and between the memory and logic components. Stacked DRAM dies are connected to other functional dies through TSVs (Through Silicon Vias), Microbumps, and an Interposer.

Manufacturing and Process Control in the 3D Era

This tri-layered 3D evolution profoundly impacts semiconductor manufacturing processes and associated metrology. Complex 3D structures must be precisely fabricated, posing new and challenging critical dimensions to measure. Introducing new materials across different process steps necessitates analysis for composition, concentration, contamination, and strain.

While this increase in process steps and complexity expands the scope and intensity of metrology, the objectives of high-yield and cost-effective manufacturing of advanced semiconductor devices remain paramount. As far as metrology is concerned, achieving these objectives is facilitated through multidisciplinary metrology, Link- https://www.novami.com/products/products-overview innovative migration of traditional lab tools to HVM in fabs (e.g., XPS, Link-  https://www.novami.com/nova-technology/x-ray-photoelectron-spectroscopy-xps/ Raman, Link- https://www.novami.com/nova-technology/raman-spectroscopy/ SIMS Link- https://www.novami.com/nova-technology/secondary-ion-mass-spectrometry-sims/ ), the development of Machine Learning Link- https://www.novami.com/nova-product/nova-fit/and advanced 3D modeling algorithms, and the introduction of out-of-the-box Hybrid Metrology  Link- https://www.novami.com/nova-technology/hybrid-metrology/ solutions for highly complex metrology challenges.

technology solutions to these ever-evolving challenges, supporting the semiconductor industry's continuous growth. If you're eager to contribute to this exciting journey, explore opportunities on our career page today! Link to Career Site https://www.novami.com/careers/working-at-nova/

Images credits:

[1] 3-D Self-aligned Stacked NMOS-on-PMOS Nanoribbon Transistors for Continued Moore’s Law Scaling; Authors: multiple (Source: IEEE Link- https://ieeexplore.ieee.org/document/9372066)
[2] Development of three-dimensional MOS structures from trench-capacitor DRAM cell to pillar-type transistor; Author: Hideo Sunami (Source: IEEE) Link- https://www.semanticscholar.org/paper/Development-of-three-dimensional-MOS-structures-to-Sunami/b441177720b61520c69fe27cdb29ea5eb8ba31a3
[3] 1T-1C Dynamic Random Access Memory Status, Challenges, and Prospects Authors:  Alessio Spessot and Hyungrock Oh (Source: IEEE  Link- https://ieeexplore.ieee.org/document/8976234