Abstract:

One of the many constrains of High Numerical Aperture Extreme Ultraviolet Lithography (High NA EUVL) is related to resist thickness. In fact, one of the consequences of moving from current 0.33NA to 0.55NA (high NA) is the Depth of Focus (DOF) reduction. In addition, as the resist feature lines shrink down to 8nm half pitch, it is essential to limit the aspect ratio to avoid pattern collapse. The direct consequence of such a situation is that a resist thickness of 30nm,usually used for 32nm pitch dense line/space (LS), will not be suitable for 16nm pitch, where the target thickness is expected to be 15nm thickness or less to ensure a similar aspect ratio. The question we need to answer is how the resist thickness reduction will impact the various metrology techniques needed to properly set up a process. To address this question, a set of wafers using both Chemical Amplified Resist (CAR) and Metal Oxide Resist (MOR) at different thicknesses and with different types of underlayer have been generated for LS patterns at 32nm pitch. We first investigated the impact of film thickness by scanning electron microscope (SEM) on the imaging of CAR resist lines. To start with, our current Best-Known Methods (BKM’s) were used to acquire the SEM images. As resist thickness decreases, noise level and image contrast are observed to degrade dramatically. Such an image quality degradation may directly impact the quality of the CD measurements both in terms of accuracy and precision. In this paper we investigated the thin resist wafer set described above using various techniques, such as Critical Dimension Scanning Electron Microscope (CD SEM), Atomic Force Microscopy (AFM), Low Voltage SEM (LV SEM), scatterometry, Pattern Shift Response (PSR), and optical defect inspection. The impact of the resist thickness is estimated for each approach, and optimal settings were investigated to minimize the relative impact on metrology. Our results indicated that, in most cases, alternative operation conditions and BKM settings, sometimes drastically different from the usual operation condition, must be used to guarantee the metrology requirements. Our results show that, despite the impact of thinning resist materials, it is possible to find appropriate settings to strengthen the metrology quality output.

Keywords: Thin Resist, High NA EUVL, e-beam, CD SEM, Scatterometry, AFM, inspection, PSR

Abstract
Magnetoresistive random-access memory (MRAM) technology and recent developments in fabrication processes have shown it to be compatible with Si- based complementary metal oxide semiconductor (CMOS) technologies.

The perpendicular spin transfer torque MRAM (STT-MRAM) configuration opened up opportunities for an ultra-dense MRAM evolution and was most widely adapted for its scalability. Insertion of STT-MRAM in the back end of line (BEOL) wiring levels has many advantages, including density, latency, and endurance with the promise of being comparable to performance of dynamic random access memory technology (DRAM).

There are several important parameters at multiple process steps which require precise metrology for STT-MRAM integration.
Inline metrology of the magnetic tunnel junction (MTJ) pillar is vital to calibrate the magnetic read/write performance parameters. This work discusses various challenges to monitor critical process steps for integrating STT-MRAM in advanced CMOS technologies and key metrology solutions are presented.

To precisely predict MRAM junction resistance early in the process flow, a machine learning model was developed using scatterometry spectra collected after MTJ pillar formation and corresponding resistance data from the end of line electrical test.
This machine learning model utilizes metrology data from the pillar formation process and can predict accurate device resistance values.
Additionally, carefully monitoring the required planarization process of an interlayer dielectric deposited after the MTJ pillar formation is critical to avoid subsequent defects.
Several modelling techniques are discussed and a new spectral interferometry-based technique, vertical travelling scatterometry (VTS), is demonstrated as a solution for measurements on fully integrated device areas.

ABSTRACT

In this work, a novel spectral interferometry technique called vertical travelling scatterometry (VTS) is introduced, demonstrated, and discussed. VTS utilizes unique information from spectral interferometry and enables solutions for

applications that are infeasible with traditional scatterometry approaches. The technique allows for data filtering related to spectral information from buried layers, which can then be ignored in the optical model. Therefore, using VTS, selective measurements of the topmost part of an arbitrarily complex stack are possible within a single metrology step. This methodology helps to overcome geometrical complexities and allows focusing on parameters of interest through dramatically simplified optical modelling. Such model simplifications are specifically desired for back-end-of-line applications. Three examples are discussed in this paper: monitoring (i) critical dimensions of a first metal level on top of nanosheet gate-all-around transistor structures, (ii) the thickness of an interlayer dielectric above embedded memory in the active area, and (iii) critical dimensions of trenches on top of tall stacks in the micrometer range comprising many layered dielectrics. It was found that, in all three cases, data filtering through VTS allowed for a simple optical model capable of delivering parameters of interest. The validity and accuracy of the VTS solution results were confirmed by extensive reference metrology obtained by traditional scatterometry, scanning electron microscopy, and transmission electron microscopy.

Keywords: Vertical Travelling Scatterometry, Scatterometry, OCD, Spectral Reflectometry, Spectral Interferometry

Abstract—Methodologies for characterization of the lateral indentation of silicon-germanium (SiGe) nanosheets using different non-destructive and in-line compatible metrology techniques are presented and discussed. Gate-all-around nanosheet device structures with a total of three sacrificial SiGe sheets were fabricated and different etch process conditions used to induce indent depth variations. Scatterometry with spectral interferometry and x-ray fluorescence in conjunction with advanced interpretation and machine learning algorithms were used to quantify the SiGe indentation. Solutions for two approaches, average indent (represented by a single parameter) as well as sheet-specific indent, are presented. Both scatterometry with spectral interferometry as well as x-ray fluorescence measurements are suitable techniques to quantify the average indent through a single parameter. Furthermore, machine learning algorithms enable a fast solution path by combining x-ray fluorescence difference data with scatterometry spectra, therefore avoiding the need for a full optical model solution. A similar machine learning model approach can be employed for sheet-specific indent monitoring; however, reference data from cross-section transmission electron microscopy image analyses are required for training. It was found that scatterometry with spectral interferometry spectra and a traditional optical model in combination with advanced algorithms can achieve a very good match to sheet-specific reference data.