ABSTRACT
A systematic study of the co-optimization of target design and metrology technique is presented to accurately measure the critical dimensions of backend of line (BEOL) metal line gratings. Rigorous coupled-wave analysis calculations and machine learning approaches are combined to evaluate various design scenarios with and without patterned underlayers in conjunction with either traditional scatterometry or vertical traveling scatterometry (VTS) using spectral interferometry. It was found that for traditional scatterometry techniques employing polarized reflectometry or ellipsometry, two levels of crossed metal lines buried below the level of interest are often sufficient to suppress most of the optical contributions from any underlayer stack beneath. Alternatively, VTS utilizing spectral interferometry and signal filtering can suppress all contributions from the underlayer stack independent of the design choice thus only the top layer of interest needs to be considered in the model analysis. Machine learning models trained on VTS data instead of traditional scatterometry data can improve the accuracy and ease of setup, for example, by utilizing simplified targets for training. Three relevant BEOL cases for measurements after an etch step, a polishing step, and dielectric layer deposition on patterned metal lines are addressed.
Keywords: Scatterometry, OCD, BEOL Metrology, Spectral Interferometry, Metrology

Recent advancements in semiconductor devices are driven by the growing demand for massive computing power and high memory density in high-performance computing (HPC) and AI applications. Achieving this requires high-speed signal transmission through dense interconnects between chips and systems, leading to the adoption of 3D architectures to enhance energy efficiency in the AI era. In particular, 3D NAND heavily relies on the Hybrid Copper Bonding (HCB) process to integrate the CMOS periphery wafer with the memory array wafer, introducing new process control challenges. To address these, we identified key monitoring steps and critical monitoring parameters within HCB processes. Additionally, we categorized wafer geometry considerations into two main areas: wafer inner space and wafer outer space.
This paper explores metrology challenges and potential solutions, aligning with industry requirements at key monitoring steps in both wafer inner and outer space areas.
Keywords: 3D NAND, Hybrid Cu Bonding, Metrology technologies, Atomic Force Microscope, Scanning Acoustic Microscopy, Broadband spectral interferometry

As semiconductor technology advances, scaling transistors becomes increasingly challenging. The difficulty in defining and scaling devices is compounded by short channel effects, parasitic effects, and metal resistance, which limit gate-length scaling, device density, and metal pitch. Consequently, the complementary FET (CFET) architecture offers a solution by vertically stacking nFET and pFET transistors, thereby overcoming the limitations of n-to-p separation. This ‘folding’ approach reduces the cell active area footprint, making CFET a promising candidate for next-generation semiconductor nodes.
However, CFET adoption introduces complexities in manufacturing and process control. Tight control is needed for the Si/SiGe superlattices with multiple layers and different Ge content, both for the CFET performance and the novel middle-dielectric-insulation (MDI) process. A higher aspect ratio is used in all front-end patterning applications. The multiple novels etch-back steps require tight vertical edge placement error (vEPE). Inner spacer uniformity control also becomes more challenging.
In-line Optical Critical Dimension (OCD) is essential to control all the complex processes involved in complementary FET (CFET) manufacturing, enabling fast, non-destructive, and precise tracking of all critical parameters, enabling reduction of the wafer-to-wafer and within-the-wafer variations. The current paper presents OCD monitoring results for the development of the essential CFET process steps, starting from the superlattice formation down to the inner spacer (ISP) etch back. The required robust OCD models were created for all process steps based on the specially designed splits defining process windows, validated with the reference metrology, and applied to the pilot line process control.
Keywords: Optical Critical Dimensions (OCD), Complimentary FET (CFET), Process control.