Firmly In‑Line: Materials Metrology Powering Next‑Generation FEOL Manufacturing

At this year’s SPIE Advanced Lithography + Patterning conference, three papers demonstrated how in‑line materials metrology is becoming central to enabling today’s FEOL logic technologies. With nanosheet and GAA structures placing new demands on material characterization—whether in strain, composition, or near‑surface integrity—the industry is turning to metrology tools that deliver deeper material insight directly in the fab. The work presented this year highlights how these capabilities are maturing to support the complexity of modern logic devices.  

Model‑Based Raman for Nanosheet Devices: From Complex Signals to Optimized Sensitivity 

Nanosheet device performance hinges on channel strain and the composition/doping of epitaxially grown source/drain (S/D) regions. In complex 3D stacks, Raman peaks can overlap across Si, SiGe, and gate materials, and amplitudes become geometry‑dependent—making straightforward interpretation difficult without modeling. The goal is clear: maximize sensitivity to the property of interest (e.g., nanosheet strain or S/D Ge%) while minimizing interference from neighboring layers and process steps. 

Model‑Based Raman (MBR) for Optimized In‑Line Measurements 

MBR rigorously simulates local field distributions and scattering efficiency based on stack geometry, optical constants, and Raman tensors—so measurement configurations (wavelength, polarization, objective) can be chosen for the cleanest, most sensitive signal. In validation, simulated and measured spectra agree closely on both simplified and fully integrated structures, and MBR helps separate nanosheet/channel contributions from S/D epi or poly‑Si. It also identifies when prior information improves accuracy (e.g., assuming a stable nanosheet contribution). 

To conclude, MBR simulations decompose complex signals for 3D structures and enable in-line Raman measurements with the highest measurement selectivity to the properties of interest while minimizing interference from irrelevant contributions. More broadly, MBR establishes a physics-based framework to decouple intrinsic material properties from geometry and optics-driven measurement artifacts in advanced 3D device metrology. 

Read the full paper here: https://www.novami.com/publications/model-based-raman-simulations-for-optimized-metrology-innanosheet-transistor-devices/ 

In‑Line SIMS for Logic: Confidence in Reliability and Performance 

 SIMS is often viewed as a consumptive technique because it sputters the surface and leaves a small crater at the analysis site. However, this study shows that when applied in‑line under the conditions evaluated, SIMS does not compromise downstream processing, device reliability, or electrical performance. The work compares “SIMS‑measured” and control wafers across FEOL through M1, supported by surface analysis and in‑line electrical tests to validate this conclusion. 

What the Study Demonstrates 

Across multiple process steps and crater conditions, wafers measured with in‑line SIMS underwent lithography, device manufacturing, and electrical testing without adverse impact. Crater morphology, contamination checks, and device‑level results collectively support SIMS as a practical in‑line metrology option for logic devices. 

• No surface defects after coating typical lithography stacks; craters exhibited shallow sidewalls and uniform floors, enabling complete filling without special precautions.  
• No contamination detected around craters by AFM/XPS; tool design mitigated redeposition. Cross‑section TEM/EELS found no sputter‑related contamination. 
• No yield or device‑performance degradation observed for nanosheet and planar devices at in‑line e‑test (post‑M1). 
• Demonstrated practical in‑fab workflow benefits: fast turnaround (minutes), reproducible data, and sampling strategies that keep measured wafers in the line. 

Bottom line: When running under the described conditions and sampling strategy, in‑line SIMS did not impact device reliability or performance, addressing a central concern for fab adoption. 

Read the full paper here: https://www.novami.com/publications/model-based-raman-simulations-for-optimized-metrology-innanosheet-transistor-devices/  

In‑Line XPS on Fully Integrated Targets: From Blanket Films to Device‑Relevant Measurements 

As nanosheet gate‑all‑around devices mature, traditional blanket‑film XPS models can mischaracterize near‑surface stacks if they ignore the underlying SiGe/Si top sheet context. At the same time, fabs need XPS that can perform not only on blankets, but also on-structure measurements: extracting S/D epi composition, identifying parasitic growth, and monitoring CMP residues at device‑relevant locations. 

Advanced In‑Line XPS Modeling and XRF Measurements 

The work updates nanosheet‑aware blanket models (e.g., correcting Si/Ge intensities) and applies XPS directly on fully integrated targets, with complementary XRF when deeper volumetric sensitivity is needed. The result is device‑area characterization that tracks thin‑film and compositional changes where they matter. 

• Nanosheet‑corrected models improve Si top sheet and high‑k thickness accuracy; align XPS thicknesses with nominal XRD and linearize high‑k vs. Si variation. 
• On‑structure XPS quantifies S/D epi Ge% vs. pitch, flags parasitic nFET epi on pFET regions (via P 2p signal), and establishes CMP residue thresholds on device and OCD target areas.  
• Complementary XRF tracks buried SiGe content and pre/post process deltas. It also improves confidence where penetration depth limits apply. 

Read the full paper here: https://www.novami.com/publications/in-line-xps-for-advanced-semiconductor-manufacturing-and-metrology-on-fully-integrated-targets/ 

Materials Metrology at the Center of Logic Scaling 

These papers underscore a clear trajectory in logic manufacturing: materials metrology—once the domain of lab instruments—is now firmly in‑line and in‑fab. Techniques such as Raman, SIMS, and XPS are not only being deployed on production wafers; their applications and models are evolving to keep pace with shrinking geometries and complex 3D stacks. Model‑based Raman tunes measurement configurations for maximum sensitivity in nanosheet devices; XPS adopts nanosheet‑corrected models and extends confidently to fully integrated targets; and in‑line SIMS demonstrates that depth‑profiling can be run without degrading reliability or device performance—strengthening confidence in its role as a viable metrology solution on the line. Together, these trends highlight how lab‑grade materials analysis is becoming standard, scalable metrology for logic nodes, and how continued model development will remain essential as integration advances.