The high-resolution compositional depth profiles generated by SIMS can provide invaluable process insights inaccessible through other techniques. Recently, inline SIMS was introduced, which embodies specific design considerations for in-fab use.1 In this paper, possible impacts on production wafers are investigated by evaluating the potential contamination and performance-impacting defects arising from ion sputtering. Post-analysis assessments include planarization effectiveness prior to lithography, surface contamination evaluations, and electrical tests to evaluate transistor performance. It was found that craters resulting from sputtering exhibit shallow sidewall angles, allowing for effective filling by typical planarization layers coated prior to lithography with no negative impact on subsequent processing. Additionally, no evidence of surface contamination in the vicinity of the craters was observed. In-line electrical tests showed no performance or reliability impact on gate-all-around nanosheet transistors related to sputtering performed after various processing steps through front-end-of-line manufacturing. Overall, the results demonstrate that inline SIMS may be implemented as an in-line metrology solution and wafers can continue through the manufacturing line without impact on device performance.
Keywords: inline metrology, SIMS, semiconductor wafers, manufacturing, silicon, transistors